As the demand for cheaper, faster, lower power consuming microprocessors increases, so must the device packing density of the integrated circuit. Very large scale integration (VLSI) techniques have continually evolved to meet the increasing demand. All aspects of the integrated circuit must be scaled down to fully minimize the device dimensions of the integrated circuit. In addition to minimizing transistor dimensions, one must minimize the dimensions of the electrical interconnections which integrate the semiconductor devices, such as transistors, together on a microchip in order to form a complete circuit.
Currently, aluminum alloys are the most commonly used conductive materials for electrical interconnections in a VLSI integrated circuit. Aluminum and its alloys have been fully characterized for use as electrical interconnections, and much technology has been developed to aid in the formation of aluminum interconnections. While aluminum has very attractive features for use as an electrical interconnection such as low electrical resistivity and strong adhesion to silicon dioxide (SiO.sub.2), as VLSI dimensions reach into the deep-submicron Ultra Large Scale Integration (ULSI) regime, the deficiencies of aluminum and its alloys become limiting factors in achieving superior performance. For example, as the width of electrical interconnections becomes narrower, the resistance of aluminum becomes non-negligible and begins to contribute significantly to the resistance-capacitance (RC) time delay of the circuit. Additionally, with decreasing dimensions, design rules become increasingly restricted by aluminum interconnection reliability concerns such as electromigration, stress-induced void formation, hillock suppression, and current density limitations.
For these reasons, the microelectronics industry has recently migrated towards the investigation of more robust, more conductive metals for use in interconnection technology such as Copper (Cu). Cu is approximately 40% lower in resistivity than Al and is much more resistant to reliability problems such as electromigration. One of the main reasons why the use of Cu and its alloys for interconnection applications has not been more widespread is because a manufacturable dry-etch process has not yet been demonstrated that can pattern Cu-based materials using standard photolithographic techniques. Therefore, to implement the use of Cu as a microelectronic interconnection material it has become necessary to develop alternate patterning techniques.
One technique is known as damascene. In damascene, a dielectric layer is deposited onto a substrate, patterned, and etched back such that the grooves, vias, or other recessed regions etched into the dielectric layer represent the desired metal interconnection pattern. A conductive material is then deposited over the entire surface of the device, filling the recessed regions and blanketing the surface of the dielectric layer. Next, the conductive material is etched back to a degree such that the conductive material becomes electrically isolated within the recessed regions etched out of the dielectric layer.
An inadequately filled recessed region in a damascene process flow leads to the creation of a void or tunnel. Voids significantly degrade semiconductor device yields thereby adding to the total manufacturing cost. FIG. 1a shows a semiconductor substrate 105 with dielectric layers 100 and 101 deposited on its surface. FIG. 1b shows the semiconductor substrate of FIG. 1a after a groove 102 has been created in dielectric layer 100. FIG. 1c shows the semiconductor substrate of FIG. 1b after a conductive layer 103 has been deposited on its surface. Note that gap 104 is beginning to form in the conductive layer 103.
As conductive material is deposited onto the substrate of FIG. 1b, the conductive material may be deposited at a faster rate on the top surface and along the walls nearer the top surface of dielectric layer 100 within groove 102 then at the bottom of groove 102. As a result, gap 104 is formed. As the walls of gap 104 close in near the top of groove 102, it becomes increasingly more difficult for the conductive material to travel to the bottom of gap 104 without "touching" and sticking to the upper walls of gap 104. The amount of conductive material deposited nearer the mouth of gap 104 is determined by how well the conductive material sticks to the substrate upon contact with it. If it sticks easily, as with sputter deposition, then less conductive material will be deposited sit the bottom of gap 104 compared to the amount of conductive material deposited nearer the mouth of gap 104. This causes a bulging or cusping effect at the mouth of gap 104 as can be seen in FIG. 1c. If the top surface of the substrate is etched back at this point, gap 104 will remain inside groove 102 leading to the problems described below as well as limiting the current carrying capability of the electrical interconnection. Therefore, it is necessary to continue depositing conductive layer 103 in order to better fill groove 102 with conductive material.
FIG. 1d shows the result of continued deposition of a conductive material when the sticking coefficient is high. Note the cusping of the walls at the mouth of gap 104. The result of this cusping is that the bottom of the gap has been sealed off from the surface of the substrate. Thus, the gap has evolved into a tunnel traveling along groove 102. Such a tunnel is known as a void. Gaps and voids can cause significant problems in a semiconductor manufacturing process and are considerable issues for sputtered and evaporated films. One problem with gaps and voids is that they can trap impurities which can harm the semiconductor device in subsequent process steps. For example, FIG. 1e shows the semiconductor substrate of FIG. 1d after the surface of conductive layer 103 has been etched back to isolate the portion of conductive layer 103 residing within groove 102 of dielectric layer 100. The isolated conductive layer 103 will become an electrical interconnection of the device. Note that void 104 still exists within the electrical interconnection 103.
Assuming conductive layer 103 of FIG. 1d was etched back using some sort of chemical etching process, the etchant chemicals may become trapped within the gap or hollow void 104 and cause additional etching or corrosion of electrical interconnection 103 even after the etchant has been removed from the surface of the substrate. These trapped etchant chemicals may then contaminate the semiconductor device which could degrade reliability. Trapped etchant chemicals may also continue to etch the electrical interconnection 103 resulting in the thinning of electrical interconnection 103 or the creation of a electrical open, thereby resulting in a failure. Interconnection thinning may lead to reliability problems such as electromigration and current-carrying limitations. Additionally, trapped contaminants may expand upon subjecting the semiconductor substrate to subsequent high temperature processing steps. Such expansion could cause significant damage to adjoining surface features of the semiconductor device. Finally, trapped contaminants may escape during a subsequent process step conducted within a process chamber, thereby contaminating all other semiconductor devices within the chamber.
Note that the potential for forming voids is greatly increased by attempting to fill grooves of significantly varying widths together on a single substrate at the same interconnection level using deposition processes with relatively high sticking coefficients. This is because these deposition processes are typically optimized to fill a groove of a particular width. While such optimization techniques may be suitably employed to fill interconnections of this particular width on a semiconductor substrate, the problem is that grooves of widths for which the process has not been optimized run a much higher risk of void formation. This makes interconnection technology dependent on individual device layout. Such dependence degrades the manufacturability of such processes.
It is currently more desirable to form copper interconnections on a semi conductor substrate by Cu sputtering rather than by CVD of Cu. One reason why Cu sputtering is more desirable is that there is a significant cost associated with performing CVD of Cu. Equipment necessary to form CVD Cu layers is currently under development and not yet readily available for high production manufacturing environments. Additionally, the materials necessary to deposit CVD Cu layers are expensive, still under investigation, and the films are not likely to be very pure. Therefore, CVD of Cu is expensive and considerably adds to the total manufacturing cost of a semiconductor device. Also, it is not yet known if certain important alloys of Cu are capable of being deposited using a CVD system. Furthermore, while some CVD techniques which exhibit low sticking coefficients may be capable of minimizing void formation, seams are still formed along the center of the CVD layers within the grooves. Seams are formed when deposited materials on laterally opposing walls within a groove grow into each other. These seams may be undesirable due to, for example, their negative impact on the grain size of the conductive layer and their susceptibility to trapping impurities. Finally, CVD techniques which exhibit low sticking coefficients also exhibit low deposition rates. Therefore, in the interest of manufacturability, higher sticking coefficient CVD processes are typically used to accelerate throughput time. However, these higher sticking coefficient CVD processes exhibit the same short-comings as the high sticking coefficient processes discussed above.
Existing sputter deposition systems can easily and cheaply deposit Cu layers and the alloys of these layers. However, sputter deposition systems have exhibited significant limitations in their ability to fill recessed regions in a damascene process flow as discussed above. These limitations have restricted the applicability of sputter deposition systems in a damascene process.